xilinx - modular exponentiation in vhdl -

I need to implement a modular exponation in vhdl for a Spartan 6, with Google for the following paper The description of fast implementation was found in a virtex 4

I think it can be used on a Spartan 6, but I can not find the source code anywhere I found this datasheet form Helian tech too. , But it is much slower than the above. Paper on the basis of

, it does not appear that used any Virtex-4 specific attributes , So that the implementation can fit into a Spartan 6, depending on the resources needed for SLICE, BRAM, and DSP 48.

The resource overview is shown in the "Table 3. Display of our Modular Expenditure" paper, says SLICE: 3937, Bram: 7, DSP 48: 17, in Virtex-4 resources. Both Brahm in Virtex 4 and Spartan 6 have 18 kbs, and DSP 48 is both both "18x18 multiplier, one connector and one accumulator", so these resources are similar and it is advisable to compare expectations.

The SLICE structure is different in Virtex 4 and Spartan 6, so the logic requirements can be compared by going to the number "Logic Cells", compare apples to apples. In Virtex 4, there can be about 8900 logic cells (2.25 logic cell / SLICE in VirTx 4) of 3937 SLICE, which then changes into Spartan 6 (6.4 logic cell / SLICE) in 1384 SLICEs.

So to fit, designed in Spartan 6, you can search for a tool with SLICE: 1384, Bram: 7, DSP 48: 17.

Note that the "back of envelope" is counted above, and the subtle details or specific device fittings may vary as a result, but the approach is useful to determine that it looks like a possible solution.