digital logic - Strange component in quartus RTL viewer using verilog -

I am learning verilog, and when I do not know how the circuit will work only in the virog code, I see the digital logic Visit RTL viewer for But this code shows a strange element and I do not know what this component is. What is flip flop, max or logic port? Below is the code and an image, in the image, the component is the red triangle.

Code:

  module testesoma (clock, reset, in, out, aux); Input wire reset, clock, in; Output reg [3: 0] Outside, aux; Always @ (pause clock or paused reset) starts (reset) = 0; End and out = aux; Aux = aux + 1; End element  

What a great schematic: 1 to go into the trouble of generating it. You have several issues with your code, and this is a great example of blocking assignments, feedback, and not just synthesis templates, and similar threats. Quartus has definitely got spoiled, but considering the input it is not surprising. Problems:

1. Do not use blocking assignments here - & lt; Use <= code>
2. to sort your start and end s in the form of nervousness, in your code start / end unless it is necessary; It's verbose, and hides such errors. Use only when you need to explicitly create a multi-stem block start / end note that aux = aux + 1 your clock Outside is if / else statement - when to execute it?
3. When you want to have feedback like aux = aux + 1 , be careful.
4. Be very careful. If you are not careful, the actual hardware will delay.
5. Do not write an infected argument like this - think parallel. Quartus is good enough, but the circuit that has been created will have to move only, and aux is not the output clock, which is probably your intention. The quartus has put it in a red buffer because it can see that it has created an unstable reaction circuit, and it has a half heart to break. There should be a warning produced about it somewhere.

   1 - Write your code again; Like some

     always @ (reset posedge clock or posedge) if (reset) out & lt; = 0; And out & lt; = Aux; Always @ (pause clock or paused reset) if (reset) aux & lt; = 0; The second aux & lt; = Aux + 1'b1;  

   2 - In a clocked always until you can not understand what could be wrong with it (hint: all < / Em> Branches / execution paths, confirm that all the variables you specify in the path possible all ) is something logical

   3 - Find out the book on Delta Delay / Assignment on VHDL, and your Verlog will be better