Interrupts execution context -

I am trying to understand this basic scenario:
suppose my CPU got an exception or an interval is. What I know, is that the CPU starts to start an interrupt service routine (IDT table is found on the idtr register to locate the ID, and the IRR gets the proper entry to get the address), but What's the code going on?

Which means that I have a thread which is currently running and is produced in some kind of middle form, in which there is an initial starting process, in the initial process, "holds" thread In another magical thread?

Thank you!

Interesting question, which raises some different issues

The first is that the interrupt does not actually run inside any thread from the CPU's perspective. In fact, the CPU itself is aware of the thread;

The second is that ISR (Interrupt Service) (ISR) (interrupt service routines) are usually run at a higher level of privilege; You do not really say that you are talking about the family of which processor, so it is difficult to be specific, but modern processors usually have at least one special mode that they enter for interrupts - Anyone with your own register bank can often ask as part of your question, whose page table is active during an interrupt?

The third question is, whose memory map is with ISR when they enter the answer, then, the process is going to be highly specialized; It is possible to visualize the architecture that disables paging on the ISR entry, other architectures that automatically switch on an interrupt page table, and (perhaps the most common approach), which when entering an ISR, Decide not to do anything about it.

The fourth is that there are some operating systems policies on a common approach to modern operating systems, ISR itself is as low as possible, and where anyone Also important is to do the job, change the barrier in any kind of event, which can be controlled by the kernel thread (or possibly, maybe a user thread)) In Rnali, code that handles really Interrupt he may well run in a specific thread, although it is in fact the point is not really an interrupt service routine.

Summary:

• In the context of any given thread, ISR itself does not run actually .
• ISR may be running with page table interrupted thread (depends on architecture).
• ISRs may be start with a copy of the registers of that thread (depending on the architecture).
• In modern systems, ISR usually tries to schedule a program and then quickly exit. That event can be controlled by a particular thread (such as for processor exceptions, it is usually given as a signal or structured exception or is due to the thread due to which);

If you are interested in special for x86 (i think that you are, as you use some intel specific terms in your question), you will see volume 3b, You need to look at and you will need to see the operating system documentation. X86 is a very complex architecture compared to some others - for example, it can optionally switch a function on an interactive delivery (if you put "Task gate" in the IDT) , Then in that case there is definitely a set of registers and possibly its own page table; Even if this feature is used by a given operating system, there is no guarantee that x86 functions directly map (or at all) directly to the operating system processes and / or threads.